1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method of the semiconductor device. In particular, the present invention is relates to a semiconductor device used for millimeter wave power amplifiers, such as GaN based FETs (field effect transistors) and GaAsFETs, and having air-tightness, and a fabrication method of the semiconductor device.
2. Description of the Related Art
A semiconductor device used with a high frequency band, for example, a microwave power amplifying device, is composed of circuit elements such as: active elements, such as a field effect transistor; passive elements, such as a resistor and a capacitor; and micro strip-lines for transmitting high frequency signals.
The above circuit elements are formed, for example, on a semi-insulating substrate. An electrode for grounding is formed in a backside of the semi-insulating substrate. And, when grounding the circuit element provided on the semi-insulating substrate, the electrode for grounding formed on the backside of the semi-insulating substrate is electrically connected with the circuit element through a VIA hole (via hole) which passes through the semi-insulating substrate, for example (for example, refer to Patent Document 1 and Patent Documents 2).
On the other hand, as a method of packaging holding air-tightness applicable in contrast with such the semiconductor device, “MICROSTRUCTURE, SEALING METHOD OF THE MICROSTRUCTURE, MICRO ELECTRIC MACHINE ELEMENT AND FABRICATION METHOD OF THE MICRO ELECTRIC MACHINE ELEMENT, AND ELECTRONIC APPARATUS” are disclosed (for example, refer to Patent Document 3). In the Patent Document 3, the aim is to providing a microstructure and a micro electric machine element which enabled to form an airtight structure easily by using a semiconductor process. An enclosure wall is formed on a substrate so that a body of the micro electric machine element may be surrounded, a top film is bonded to the upper surface of the enclosure wall, and the body of the micro electric machine element is sealed.
Moreover, as a method of packaging holding air-tightness, in an example of a thin film piezoelectric resonator, a filter, and a thin film piezoelectric resonator, “THIN FILM PIEZOELECTRIC RESONATOR, FILTER, AND FABRICATION METHOD OF THE THIN FILM PIEZOELECTRIC RESONATOR” is disclosed (for example, refer to Patent Document 4). In the Patent Document 4, the aim is to providing a thin film piezoelectric resonator which includes a sealing structure which can prevent a collapse of a cavity and can adjust resonance frequency with high precision. The thin film piezoelectric resonator includes: a substrate having a cavity on the surface; a lower electrode extended on the cavity from on a substrate; a piezoelectric film provided on the lower electrode; an upper part electrode which opposes with the lower electrode and is placed on the piezoelectric film, and also is extended on the substrate from on the piezoelectric film; and a sealing member which includes a resonance part inside specified in a region in which the lower electrode and the upper part electrode oppose, is provided on the substrate so that an opening which extends from the cavity may be located outside, and closes the resonance part.
FIG. 1 shows a configuration diagram of an overall schematic plane pattern of a semiconductor device according to a conventional example.
As shown in FIG. 1, the overall schematic plane pattern configuration of the semiconductor device according to the conventional example includes: a substrate 10; a gate electrode 24, a source electrode 26, and a drain electrode 22 which are placed on a first surface of the substrate 10 and have a plurality of fingers, respectively; gate terminal electrodes G1, G2, . . . , G4, source terminal electrodes S1, S2, . . . , S5 and drain terminal electrode D which are placed on the first surface of the substrate 10, governed and formed a plurality of fingers, respectively, every the gate electrode 24, the source electrode 26, and the drain electrode 22.
In a configuration example of FIG. 1, as for the size of each part, for example, cell width W1 is about 120 micrometers, W2 is about 80 micrometers, cell length W3 is about 100 micrometers, W4 is about 120 micrometers, and gate width is about 2.4 mm (=100 micrometer×6×4 cells) as a whole.
In the example of FIG. 1, in the source terminal electrodes S1, S2, . . . , S5, VIA holes are formed from a back side of the substrate 10, and a ground conductor is formed on the backside of the substrate 10. And, when grounding the circuit element, the circuit element provided on the substrate 10 and the ground conductor formed on the backside of the substrate 10 are electrically connected through the VIA holes SC1, SC2, . . . , SC5 which pass through the substrate 10.
In addition, the gate terminal electrodes G1, G2, . . . , G4 are connected to a surrounding semiconductor chip by a bonding wire etc., and the drain terminal electrode D is also connected to a surrounding semiconductor chip by a bonding wire etc.
FIG. 2A shows a package configuration of the semiconductor device according to the conventional example and is a schematic plane pattern configuration diagram, FIG. 2B shows a schematic section structure chart taken in the line I-I of FIG. 2A, and FIG. 2C shows a schematic section structure chart taken in the line II-II of FIG. 2A, respectively.
As shown, for example in FIG. 2, the package configuration of the semiconductor device according to the conventional example includes: a substrate; a field effect transistor 18 placed on the substrate; input/output matching circuits 17 placed at input/output sections of the field effect transistor 18, respectively; input/output strip-lines 15 connected to the input/output matching circuits 17, respectively; an enclosure wall 12 which includes the field effect transistor 18, the input/output matching circuits 17, and a part of the input/output strip-lines 15; and an upper surface package sealed part 16 placed on the enclosure wall 12 through an adhesive part 14.
In the semiconductor device according to the conventional example, the semiconductor element itself did not have air-tightness but the package which mounts a semiconductor element had air-tightness. Moreover, a high damp-proof dielectric film was deposited on the gate electrode of the semiconductor element.    Patent document 1:    Japanese Patent Application Laying-Open Publication No. H02-288409    Patent document 2:    Japanese Patent Application Laying-Open Publication No. 2001-28425    Patent document 3:    Japanese Patent Application Laying-Open Publication No. 2006-43847    Patent document 4:    Japanese Patent Application Laying-Open Publication No. 2007-36829
The airtight package applied to the semiconductor device of the conventional example is high-cost.
Moreover, the airtight package applied to the conventional semiconductor device had to bond a terminal with the enclosure wall in order to also give air-tightness to a terminal area, therefore had great influence on the high frequency characteristics of the terminal.
On the other hand, although there is also a method of applying resin on the gate electrode in order to give air-tightness to the semiconductor device itself, this method has a problem of increasing gate capacitance and reducing gain of the semiconductor device.